Leading optical technology experts, Ayar Labs, has been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES research project. The goal of PIPES (Photonics in Package for Extreme Scalability) is to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology.
In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging. According to Vince Hu, VP of Strategy and Innovation for Intel’s FPGA products, to meet the growing datacenter workloads that have an insatiable demand for bandwidth and the need to connect devices at rack-scale distances, the best method is an optical interconnect using an Ayar Labs chiplet(s), through which Intel can achieve very high bandwidth at low latency and low power consumption.
According to Charles Wuischpard, CEO of Ayar Labs, bringing optical connectivity all the way into the CPU/SOC package has long been one of the ‘Holy Grail’ projects in High Performance and Hyperscale Computing, as it unleashes the performance of ever more powerful computing and network processors and removes a major bottleneck and set of constraints in systems architecture and design. Moreover, the energy consumed in moving data through a system is now very significant and growing, and the best way to manage that is to move the data optically from end to end.
The TeraPHY chiplet is manufactured on GLOBALFOUNDRIES state-of-the-art 45nm platform, which enabled Ayar Labs to build a monolithic, single-die solution that integrates both electrical and optical photonic circuits and devices on a single chip.
Ayar Labs also demonstrated the TeraPHY solution at the Supercomputing 2019 Conference in Denver, CO. The company has also announced its Customer Sampling Program with select semiconductor, OEM systems builders, Telco Equipment Manufacturers, and end-users starting in early Q1 2020. The program is geared towards demonstrating both the capability of the technology as well as cementing co-design partnerships for future systems architectures in compute, network, and memory.