DSP-Driven High-Performance Clock Sources Radically Alter System Timing Architectures

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System designers have been able to provide a limited degree of data rate flexibility while still employing existing clock source technology. These designs are typically faced with the challenge of multiplying a low frequency network synchronization clock up to multiple high-frequency reference clocks as shown in Figure 1. Additionally, the timing subsystem must monitor the health of the network synchronization clocks while providing the capability to hitless switch between input references without causing phase transients on the transmit reference clock.