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Sony, in partnership with neuromorphic vision systems expert, Prophesee S.A., has jointly developed the industry’s smallest pixel size (4.86μm pixel) stacked event-based sensor with a high HDR performance rate (124dB or more). The new sensor and its performance results were announced at the International Solid-State Circuits Conference (ISSCC) 2020 held in San Francisco in the United States.
This stacked event-based vision sensor detects changes in the luminance of each pixel asynchronously and outputs data including coordinates and time only for the pixels where a change is detected, thereby enabling high efficiency, high speed, low latency data output. It achieves high resolution, high speed, and high time resolution despite its small size and low power consumption.
This accomplishment was made possible by combining technical features of Sony's stacked CMOS image sensor, resulting in small pixel size and excellent low light performance that are achieved by the use of Cu-Cu connection (technology that provides electrical continuity via connected Cu (copper) pads when stacking the back-illuminated CMOS image sensor section (top chip) and logic circuits (bottom chip)), with Prophesee's Metavision event-based vision sensing technologies leading to fast pixel response, high temporal resolution and high throughput data readout.
The newly developed sensor is suitable for various machine vision applications, such as detecting fast moving objects in a wide range of environments and conditions.
MAIN FEATURES:
- Small Size and High Resolution Delivered by Industry's Smallest 4.86μm Pixel Size: The pixel chip (top) and the logic chip (bottom) incorporate signal processing circuits which detect changes in luminance based on an asynchronous delta modulation method are arrayed separately. Each pixel of the two individual chips is electrically connected using Cu-Cu connection in a stacked configuration. In addition to the industry's smallest 4.86μm pixel size, the sensor also delivers 1/2 type, 1280x720 HD resolution by achieving high density integration with a fine 40nm logic process.
- Industry's Highest 124db (Or More) HDR Performance Achieved By High Aperture Ratio: The industry's highest 124dB (or more) HDR performance is made possible by placing only back-illuminated pixels and a part of N-type MOS transistor on the pixel chip (top), thereby allowing the aperture ratio*3 to be enhanced by up to 77%. High sensitivity/low noise technologies Sony has developed over many years of CMOS image sensor development enable event detection in low-light conditions (40mlx).
- Event Data Readout with High Time Resolution and High Output: While a frame-based sensor outputs entire images at fixed intervals according to the frame rate, an event-based sensor selects pixel data asynchronously using a row selection arbiter circuit. By adding time information at 1μs precision to the pixel address where a change in luminance has occurred, event data readout with high time resolution is ensured. Furthermore, a high output event rate of 1.066Geps has been achieved by efficiently compressing the event data, i.e. luminance change polarity, time, and x/y coordinate information for each event.

KEY SPECIFICATIONS:
- Process Technology: 90nm BI CIS on 40nm CMOS
- Power Supply Voltage: 2.5, 1.1(V)
- Resolution: 1280×720
- Pixel size: 4.86 x 4.86(µm2)
- Fill factor: >77%
- Power Consumption: 100kEPS - 32(mW), 300MEPS - 73(mW)
- Power/Pixel: 35(nW)
- Energy/Event: 137(pJ)
- Max Event Rate: 1066(MEPS)
- Timestamp Resolution: 1(µs)
- Contrast Sensitivity NCT: 15.7(% contrast)
- Low-light Cutoff: 40(mlx)
- Dynamic Range: >124dB