A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
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A review on high-resolution CMOS delay lines: towards sub-picosecond jitter performance
- Author:
Bilal . Abdulrazzaq, Izhal Abdul Halin, Shoji Kawahito , Roslina M. Sidek , Suhaidi Shafie and Nurul Amziah Md. Yunus
CMOS delay lines with a focus on the most frequently used techniques for high-resolution delay step is presented. The primary types, specifications, delay circuits, and operating principles are presented. The delay circuits reported in this paper are used for delaying digital inputs and clock signals. The most common analog and digitally-controlled delay elements topologies are presented, focusing on the main delay-tuning strategies
