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Implant Metrology for Bonded SOI Wafers Using a Surface Photo-Voltage Technique

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Implant Metrology for Bonded SOI Wafers Using a Surface Photo-Voltage Technique

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  • Author: Adam Bertuch, Wesley Smith, Ken Steeples, Robert Standley, Anca Stefanescu, Ron Johnson
This paper presents preliminary results of an implant monitor technology applicable to donor wafers prior to the bond-and-layer-transfer process With continued CMOS scaling, problems such as active and passive power dissipation, short channel effects and SRAM single event upsets are becoming increasingly intractible. Engineered substrates, in particular SOI wafers, provide an important avenue to managing these problems and enabling further scaling. This is driving the large-scale manufacturing of state-of-the-art, large diameter SOI wafers having very thin top silicon layers with very tightly controlled layer thickness and uniformity.

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