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Advancing System-in-Package Technology

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Advancing System-in-Package Technology

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As SiP packages contain two or more chips stacked vertically as well as horizontally, micro-vias with typical diameters ranging from approximately 200 to just a few microns are used to provide vertical electrical connections among them. These micro-vias may be present either in an interposer (which is also referred to as an IC substrate) layer or within the chips themselves. Formation of micro-vias is commonly accomplished through chemical etching, but this process has limitations. Although chemical etching is a proven methodology for silicon and glass, etching cannot be used with ceramics or organic materials. Additionally, the waste management required for chemical etching processes presents extra complications and costs.

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